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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
219
(2) Timer mode control registers 01 and 11 (TMC01 and TMC11)
The TMCn1 registers control the operation of TMn (n = 0, 1).
These registers can be read or written in 8-bit units.
These registers are set to 20H after reset.
Cautions 1. The various bits of the TMCn1 register must not be changed during timer operation. If
they are to be changed, they must be changed after setting the TMCEn bit of the TMCn0
register to 0. If these bits are overwritten during timer operation, operation cannot be
guaranteed (n = 0, 1).
2. If the ENTOn and ALVn bits are changed at the same time, a glitch (spike shaped noise)
may be generated in the TOn pin output. Either create a circuit configuration that will not
malfunction even if a glitch is generated or make sure that the ENTOn and ALVn bits do
not change at the same time (n = 0, 1).
3. TOn output is not changed by an external interrupt signal (INTPn0 or INTPn1). To use the
TOn signal, specify that the capture/compare registers are compare registers (CMSn0 and
CMSn1 bits of TMCn1 register = 1) (n = 0, 1).
(1/2)
OSTn
After the overflow, counting continues (free-running mode).
After the overflow, the timer maintains the value 0000H, and counting
stops (overflow stop mode).
OSTn
0
1
Setting of operation when TMn register overflowed
TMCn1
(n = 0, 1)
ENTOn
ALVn
ETIn
CCLRn
ECLRn
CMSn1
CMSn0
7
6
54
32
1
0
After reset: 20H
R/W
Address: TMC01 FFFFF608H
TMC11 FFFFF618H
When OSTn bit = 1, the TMCEn bit of TMCn0 remains at 1. Counting is restarted by
writing 1 to the TMCEn bit.
External pulse output is disabled.
External pulse output is enabled.
ENTOn
0
1
External pulse output (TOn) enable/disable
When OSTn bit = 0, output of the ALVn bit inactive level to the TOn pin is fixed.
The TOn pin level is not changed even if a match signal from the corresponding
compare register is generated.
When OSTn bit = 1, a compare register match causes TOn output to change.
However, if capture mode is set, TOn output does not change. The ALVn bit
inactive level is output from the time when timer output is enabled until a match
signal is first generated.
If either CCn0 or CCn1 is specified as a capture register, the ENTOn bit must be
set to 0.
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